Silicon Software, manufacturer of frame grabbers and intelligent image processing solutions, introduces two members to its microEnable 5 marathon CXP family. The ACX-SP and ACX-DP support the CoaXPress standard, which means all compatible CoaXPress camera types can be connected. The boards are suited for all CoaXPress configurations (CXP-1 to CXP-6) according to version 1.1.1.
The FPGA based microEnable 5 marathon frame grabber series has been developed for the Camera Link, Camera Link HS and CoaXPress cameras. Four CoaXPress boards are now part of the series: The A-Series, ACX-QP with four ports, ACX-DP with two ports and ACX-SP with one port as well as the programmable FPGA version VCX-QP (V-Series). The frame grabbers support color (RGB and Bayer) and monochrome area, line scan and CIS cameras across different topologies (single, dual and quad configurations) and up to 25 GB/s incoming bandwidth.
The new microEnable 5 marathon ACX-SP and ACX-DP frame grabbers consist of smaller versions with one or two camera ports for single link and dual link CXP cameras. They offer similar feature sets like the quad port frame grabber with an equally high bandwidth of 6.25 Gbit/s data rate per single CXP-6 connection.
The four ports of the microEnable 5 marathon ACX/VCX-QP frame grabbers can be connected to four different CoaXPress cameras at the same time with a multitude of pixel formats and bit depths. The VCX-QP version (V-Series) FPGA is graphically programmable with VisualApplets using data flow models. In a short period of time, developers create complex image processing pipelines for real-time, deterministic and low-latency applications. Existing FGPA hardware code (created with VHDL or Verilog) can also be integrated using VisualApplets Expert. For more details, visit the frame grabber page and/or call 888-808-3670.